https://e-sygoing.link Latest links in the Minimal category en-us Sun, 24 May 2026 00:20:38 -0400 https://e-sygoing.link/link/5767031-a-no-instruction-set-processor Benefits: simple, easily pipelined, useful in self-clocked systems, very flexible and optimizable, good memory access, highly. Problems: awkward to program. [cowlark.com] Mon, 06 Apr 2026 23:31:20 -0400 https://e-sygoing.link/go/5767031 https://e-sygoing.link/link/5767022-new-micros-inc Designs, builds: single board computers (SBC), peripherals, embedded systems, PCB design/layout, high level programming (industry leaders in Forth), custom design work; large line of stock products: from full handheld computers to development packages. Since 1980. Mon, 16 Mar 2026 23:22:16 -0400 https://e-sygoing.link/go/5767022 https://e-sygoing.link/link/5767025-triangle-digital-services-ltd Small, powerful Forth embedded computers: let you quickly design applications: controls, portable instruments, terminals, data loggers, GPS, CAN bus, multitasking, LCD and keyboard systems. High level language makes development simple and fast; needs no PROM programmer. Forth hardware and software. Wed, 29 Oct 2025 18:23:22 -0400 https://e-sygoing.link/go/5767025 https://e-sygoing.link/link/5767018-java-optimized-processor JOP is the implementation of a small java processor with the JVM fitting in a FPGA. Mon, 15 Sep 2025 00:02:29 -0400 https://e-sygoing.link/go/5767018 https://e-sygoing.link/link/5767023-enumera-inc Goal: dominate very low cost, low power, single core CPU market, and have the only ultra-high-end supercomputer on-a-chip system. Because the CPU core is so small, it is possible to put 1000s of cores and memory in one IC chip package. Sat, 19 Jul 2025 06:23:59 -0400 https://e-sygoing.link/go/5767023 https://e-sygoing.link/link/5767028-the-ultimate-risc Explains extreme, simple RISC, with only one instruction, move memory to memory; yet it is useful. Revision of paper first published in ACM Computer Architecture News. Sat, 10 May 2025 18:52:47 -0400 https://e-sygoing.link/go/5767028 https://e-sygoing.link/link/5767021-overview-of-the-e16-cpu Small, fast stack-based processor for FPGAs. CPU prototyped and debugged in ANS Forth. A simple RTL-specific language extension provides discrete event simulation for structural model of CPU and allows concise architecture representation. Thu, 01 May 2025 16:57:44 -0400 https://e-sygoing.link/go/5767021 https://e-sygoing.link/link/5767019-ptsc-patriot-scientific-corp Makes IGNITE I ROSC (Removed Operand Set Computer), PSC1000 32-bit embedded shBoom-based microprocessor line, many ISDN interface products, sophisticated antenna/radar technologies. Fri, 24 Jan 2025 22:02:53 -0500 https://e-sygoing.link/go/5767019 https://e-sygoing.link/link/5767026-stack-computers-forth Philip J. Koopman, Jr., CMU page. Many reports, studies, links. Compares: CISC, RISC, Stack systems; 2 & 3 stack systems. Excellent resource. Sat, 16 Nov 2024 21:02:57 -0500 https://e-sygoing.link/go/5767026 https://e-sygoing.link/link/5767017-sandpiper-technology Course on minimal processors: Guided Exploration of two FPGA-based CPU Designs, led by John Rible. Thu, 07 Nov 2024 20:38:19 -0500 https://e-sygoing.link/go/5767017