RISC
Beyond RISC: The Post-RISC Architecture
Today's RISC processors are so far from RISC roots that they are no longer truly RISC. [Michigan State University, Department of Computer Science]
ColdFire Development Resources
Source code for a GCC variant, with optimizations, bug fixes for Freescale Semiconductor (Motorola) variable length RISC 68K series processors; information on how to use GNU C, RTE…
Hyperstone Electronics GmbH
RISC/DSP processors, flash memory controllers and cards (and compact cards), ASIC design, IP hardware, biometric devices, digital still cameras.
John Mashey on RISC/CISC
From comp.arch debates, in one text document for easier reading, original text and formats preserved, mostly.
Reduced Instruction Set Computer
Growing article, with links to many related topics. [Wikipedia]
Reduced Instruction Set Computer
Brief, very clear definition, with links to related issues and processors. [FOLDOC]
RISC Architecture
Sophomore college project. Basic clear explanations of: What is RISC, MIPS processors, Pipelining, RISC vs. CISC, some recent developments, readings.
RISC vs. CISC
Document based on John Mashey (SGI) compilation of comp.arch debates, in one HTML document for easier reading, more so tables; original text and formats preserved where possible.
RISC vs. CISC: The Post-RISC Era
Detailed, balanced, historical analysis. [Ars Technica]
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