6 links
About Real Intent
realintent.com
Breakthrough in logic verification. Funded by very experienced people from EDA
Atrenta, Inc.
atrenta.com
The Spyglass suite of tools uses predictive analysis technique that performs structural analysis on Verilog and VHDL RTL to detect design problems in SoCs and ASICs.
Forte Design Systems
forteds.com
Develops software which aids your ASIC flow from design through verification.
Icarus Verilog Interactive
ivi.sourceforge.net
An Open Source interactive simulator frontend for Verilog and VHDL circuit simulation.